TSU Protocol: Open-Source RISC-V NPU for Edge AI The Problem AI inference needs dedicated hardware, but existing options are expensive and proprietary. NVIDIA's Grace Hopper costs $30K+. Apple's Neural Engine is locked to macOS. Qualcomm's DSP requires licensing. TSU Protocol is building the open alternative. Architecture RISC-V RV64 + 16 custom Agent-extended instructions: MatMul & Attention — hardware ops for transformer models Softmax & RMSNorm — normalization in silicon Agent Secure Enclave — hardware-isolated agent execution Mesh Network — on-chip scaling Tier Power Precision BOM Target TSU-M1 5W INT8 $150 Edge/IoT TSU-M2 20W FP16/INT8 $300 On-device AI TSU-M3 45W FP16/BF16 $550 Enterprise edge Open Source. Community-Funded. Everything is open: ISA spec, Verilog RTL, microarchitecture. No NDA. No royalties. Current Status Seeking $50K-$200K in community funding to cover our first MPW tape-out on 28nm/22nm. All funds DAO-governed — released transparently on milestone votes.…